To ensure that the synthesized scalable architectures are self-testable, and to make their tests containable (i.e. the total test time is bounded by a reasonable growth factor of the number of nodes), a new test methodology will be developed which consists of two major tasks. First, a family of containable test techniques for basic components, such as passive and active interconnection networks, will be developed. These techniques consist of a combination of test generation and design for testability. Secondly, a scheduling and optimization strategy, which executes the tests generated for all the components, will be developed. This strategy will maximize the concurrency in executing the necessary tests to ensure test containability for the entire system.

Our work in this project is innovative. It will allow the synthesis of low cost scalable heterogeneous architectures to be used for critical applications which need high reliability, availability and performance.

• A generic model of a scalable heterogeneous architecture to incorporate scalability of accelerators using COTS components such as DSPs.
• Definition and illustration of a scalable application specific protocol for radar signal processing applications.
• A technique that implicitly tests the baseline multistage interconnection network while testing the memories in a processor-memory-switch system.
• A technique that ensures reliable testing of memories in a processor-memory-switch system even if carried out by faulty processors.