Testing Digital Systems
Department of EE-Systems
University of Southern California

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Immediate job opening available for a post-doctoral researcher.

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Project Overview

Objective

Approach

High level synthesis

Our approach to synthesizing DSP circuits from behavioral descriptions consists of four aspects. First we apply behavioral transformations to the original behavioral description to transform it to a form that will lead to a more testable end result. Second, we enhance classical scheduling and module assignment algorithms to take into consideration test attributes. Third, we enhance classical register and interconnect assignment techniques to again take into consideration test conditions. The result from this process is a register level implementation of a DSP circuit. Finally, this description is processed by our Built-in Test System (BITS), developed under a previous ARPA contract, where the circuit is made self-testable by adding appropriate structures such as pattern generators, signature analyzers, boundary scan and test controller. This approach is innovative because others have not combined third generation high level synthesis procedures together with test synthesis. Most previous research applied simple and often erroneous rules-of-thumb, such as avoid self loops.

Performance Testing

Our approach on performance testing consists of four main subtasks. First, we will develop new designs of boundary scan cells and TAP controller to enable performance testing of interconnects and chips/die (external and internal testing). Second, we will develop a new clock-based design-for-test methodology to enable performance testing of high speed circuits. Third, we will develop tools to evaluate and design test pattern generator and response analyzer circuitry for self-testing. Fourthly we have extended the classical concept of robust test so that the worst case path delay is addressed, and we will develop an associated test generator, fault simulator and BIST structures to support this new and more comprehensive concept of performance testing. The approach is innovative because it will address the complete inadequacy of the existing boundary scan standard (IEEE 1149.1) in the area of performance testing. It will also provide practical DFT and BIST methodologies that will be applicable to high speed circuits due to their low impact on circuit performance. These techniques will together provide a comprehensive methodology for testing and diagnosing high performance systems.

Process Aggravated Noise (PAN) Faults

Process variations lead to variations in electrical parameters. These electrical variations can create process aggravated noise (PAN), such as crosstalk and ground bounce, in high performance circuits. This noise can result in erroneous circuit operation. We will determine the distribution of various electrical parameters (due to process variations) in die that are considered to be fault free. We will determine a family of design rules that takes into account clock rate, signal rise/fall times and the variations in electrical parameters. From this we will formulate the concept of ground bounce and crosstalk faults. We will identify new worst case design corners for evaluating the operational attributes of a circuit. We plan to develop an algorithm that will generate a series of test vectors that will generate the maximum ground bounce in a circuit. We also plan to design BIST structures for testing for crosstalk and ground bounce in VLSI circuits. Finally, we will develop BIST structures that have very low impact on circuit performance.

Recent Accomplishments

• Created an experimental setup for the integration of, evaluation of, and demonstration of our high level synthesis techniques which include testability considerations. Our work will be embedded within the TOPS (testability optimized synthesis system) developed at Stanford University. In addition, a suite of approximately 20 behavioral descriptions was created from various resources. These are being translated into a common HDL.
• Developed measures to characterize existing scheduling algorithms in high-level synthesis with respect to test resource requirements for BIST.
  With these measures in hand, we were then able to develop a scheduling framework into which we could incorporate these properties and generate schedules that lead to a low number of test resources in a data path.
• Developed a design-for-test test point insertion technique to modify the controllability of a circuit by adding transistors to a basic gate, rather than adding AND or OR gates to the circuit.
  The technique has the following beneficial attributes as compared to classical techniques: less performance degradation; can generate a near continuum of controllability values, rather than just the values 0 or 1; and has less negative impact on circuit observability. We are currently working on the problem of identifying the optimal subset of gates in a circuit which should be modified using this DFT technique.
• We developed a simple 5 element RLC model for use in simulating the effects of ground bounce in a large (several thousand) gate CMOS circuit having a single power/ground distribution system.
  This model leads to a reduction of 2-3 orders of magnitude in simulation time and memory with little loss in accuracy. Subsequently we carried out numerous Spice simulations using this model and determined that the maximum voltage surge can reach 2 volts; typical surge values are between 0.7 - 2.0 volts, large enough to create erroneous switching in some static and most dynamic circuits. This validates our basic assumption on the need to address ground bounce in a formal way.
• Developed a new extended concept of a robust test for path delays that captures the electrical effects of a circuit and thus leads to a true worst case delay situation.
  From this concept we were able to determine conditions required to ensure a pair or triplet of patterns to test for the worst case path delay. A fault simulator was then developed to process these vectors and we were able to show that classical robust test do not test for most worst case path delays. Under a different ARPA contract we are addressing the issue of DFT to ensure that a high percentage of paths can be robustly tested.

Reports

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Document last updated: Oct 3 1996