Note: Hyperlinked thesis titles are downloadable postscript files.

Name	Date	Dissertation Title
Hubert Huang	1971	Analysis of Random Test Pattern Generation for Combinational Circuits
Jhih Chang	1971	Analysis and Checking Experiments of 2-Way Sequential Machines
Danny C. C. Ko	1973	Self-Checking of Multi-Output Combinational Circuits Using Forced-Parity Technique
Prathema Agrawal	1977	Routing of Printed Circuit Cards: Density Analysis and Routing Algorithms
Ytrach Levendel	1977	Alegoric Generation of Test and Synchronizing Sequences for Digital Circuits
Neil Quinn	1977	An Analysis of a Force Directed Component Placement Procedure for Printed Circuit Boards
Salam Salloum	1979	Optimal Testing Algorithms for Symmetric Coherent Systems
Miron Abramovici	1980	Fault Diagnosis in Digital Circuits Based on Effect-Cause Analysis
Paul Carlock	1980	The Module Placement Problem: Analysis and NP-Completeness Results
Harold Carter	1980	Optimized Unidirectional Routing
S. K. Kumar	1980	Theoretical Aspects of the Behavioral Digital Circuits under Random Inputs
Keyhan Shamsa (M. S)	1981	A Hardware Router
Zayir Syed	1981	On Routing for Custom Integrated Circuits
Asad Ismaeel	1983	Roving Emulation: Theory and Analysis
M. S. Chandrasekhar	1984	Analysis and Algorithms for the Area Efficient Layout of Custom Integrated Circuits
Magdy Abadir	1985	A Knowledge Based System for Designing Testable VLSI Circuits
Xi-An Zhu	1986	A Knowledge Based System for Testable Design Methodology Selection
Rajesh Gupta	1991	Advanced Serial Scan Design for Testability
K. J. Lee	1991	Switch Level Test Generation for CMOS Circuits
J. C. Lien	1991	Design of Hierarchically Testable and Maintainable Systems
Mody Lempel	1994	Built-In Self-Test for Modeled Faults
Sen-Pin Lin	1994	A Design System to Support Built-In Self-Test of VLSI Circuits Using BILBO-Oriented Test Methodologies
Sridhar Narayanan	1994	Scan Chaining and Test Scheduling iin an Integrated Scan Design System
Rajagopalan Srinivasan	1994	Pseudo-Exhaustive Built-In Self-Test of VLSI Circuits
Ishwardutt Parulkar	1998	Optimization of BIST Resources during High-Level Synthesis
Wei-Yu Chen	2000	Test Generation for Crosstalk Noise in VLSI Circuits
Yi-Shing Chang	2001	Test Generation for Ground Bounce in Deep Micron Circuitry
Suriyaprakash Natarajan	2002	Switch-level Delay Test

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Melvin A. Breuer | Computer Engineering | EE-Systems | USCweb

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This page was last modified on Tuesday, Dec 4, 2001. | Copyright 2001, University of Southern California.

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This page represents the opinions of the author, and is not to be considered an official publication of the University of Southern California.