Task ID: 646.001
Start Date: October 1998 End Date: August 2001
Anticipated Primary Result
Concepts, techniques, and tools to generate sequences of patterns and new design corners for simulation-based validation for crosstalk induced errors in high-speed circuits implemented in sub-100 nm process technologies. Development and demonstration of the first systematic approaches to (1) generate pattern sequences for simulation-based validation, (2) identify new worst-case design corners for validation, and (3) integrate development of pattern sequences for validation and post-manufacturing test.
Background
Recent articles and anecdotal stories from industry indicate that improved techniques for validation for crosstalk are required. The technology trends predicted in NTRS point out that the severity of this problem will continue to grow in future sub-100 nm technologies. Currently, designers use rudimentary techniques to identify the sequences of patterns and design corners for use in simulation-based validation. The absence of any systematic methodology makes this process very time consuming as well as inexact. This inexactness can result in overly conservative designs and cause expenditure of effort on unnecessary re-design. It can also cause a crosstalk problem to escape identification, which, when discovered after the silicon is manufactured, must be corrected at great cost. This research will develop tools to automate generation of sequences of patterns and identification of design corners for simulation-based validation for crosstalk. The development of the proposed tools will significantly decrease the time required for validation by automating tasks that were previously performed manually. Furthermore, by taking into account transition delays and rise and fall times of signal transitions and correlations between the variations in the values of circuit parameters, the proposed methodology will result in fewer false negatives when compared with current practices and the pattern-less (i.e. static) validation technique proposed in [Shepard et al., D&T 98]. This will (a) enable more aggressive design, (b) decrease redesign effort, and (c) decrease complexity of post-manufacturing test.
Description
This team has developed a suite of analytical macromodels that describe the (a) creation of crosstalk effect at the target site, (b) propagation of crosstalk effect via circuit elements (devices and interconnects), and (c) transformation of crosstalk effect into a crosstalk (logic) error. They have demonstrated that such macromodels can be used, along with the variations in the values of circuit parameters, to identify new design corners. They have also developed a preliminary version of a timing-based test generator for crosstalk. They will develop a technique to determine the worst case design corners for a given target crosstalk effect for validation. This technique will use process variation data (variations and correlations) and the above macromodels to perform sensitivity analysis that will identify realistic combinations of parameter values that maximize the probability of creation of a crosstalk error due to the validation target.
The tool to generate pattern sequences for validation will be obtained by modifying the tool developed to generate post-manufacturing tests for crosstalk. An adaptive technique will be developed to validate a given target. This technique will perform test generation and simulation on increasingly larger regions of a circuit around the site of the validation target, using more accurate circuit models, extraction data, and increasingly precise design corners. Those validation targets that fail validation (or pass with a low margin) and are not eliminated via circuit redesign will be added to the list of crosstalk faults to be targeted for post-manufacturing tests.
Deliverables: