Task ID: 646.002
Start Date: October 1998 End Date: August 2001
Anticipated Primary Result
Techniques and tools to generate sequences of patterns for post-manufacturing test for crosstalk induced errors.
Background
According to recent articles, anecdotal stories from industry, and the NTRS roadmap, signal integrity problems due to crosstalk are currently a problem in some current chips and will become more of a problem in the future. This is due to smaller feature sizes, high frequencies associated with signal switching, reduced noise margins and process variations. If it were not for process variation, crosstalk effects that lead to erroneous circuit operations could be considered a design error and eliminated via redesign. But, with process variations and aggressive designs, it is not always feasible to validate a design at all process corners, and it has been shown that the classical corners are not the ones that lead to worst case crosstalk noise. Hence, crosstalk noise together with process variations (not spot defects) lead to a new class of fault which we have defined as a crosstalk fault. Generating tests for such faults is considerably harder than generating tests for classical faults, such as stuck-at and delay faults.
Description
Crosstalk gives rise to three types of noise; namely pulses, a reduction in the switching rate of a signal transition (slow-down), and an increase in the switching rate of a signal (speed-up). If these anomalies are sufficiently large, they can propagate to a storage device and create a permanent error. This team proposes to design and implement a PODEM-like test generation algorithm that, for a targeted crosstalk effect, will generate one or more pair of test patterns that, if applied to a circuit, would generate the largest possible crosstalk effect (pulse or speed-up, slow-down) at a memory device, i.e. maximize the probability of creating an error. To obtain both high accuracy and computational efficiency, new logic models, signal values, and cost functions will be developed. The team has already developed a new CMOS inverter model, methods to calculate inverter output response for pulse inputs, a method for collapsing CMOS gates into equivalent inverters, and a piece-wise linear model for pulses. Their test generation framework takes into account noise strengths and signal arrival times as well as layout related data that effects delay and crosstalk. They will develop macromodels to capture additional crosstalk scenarios, including (a) multi-way crosstalk, where in multiple lines couple with a single line, and (b) multi-level crosstalk, where several lines along a circuit path are coupled, each with one or more lines in its vicinity. They will also develop additional macromodels to enable propagation of crosstalk effect via a wider range of circuit elements (including dynamic gates, different types of latches, and interconnects) and under a wider range of conditions (such as the presence of crosstalk pulses at multiple inputs of a circuit element, and simultaneous presence of crosstalk pulses and crosstalk delays). A new analog cost measure will also be developed to efficiently guide the search for a test. They will also develop more efficient test generation techniques based on the following concepts. (a) Development of a timing-oriented backtrace procedure that will use simplified timing models. This procedure will identify backtrace paths to guide justification while eliminating invalid choices. (b) They will develop a FAN-like timing-based test generator. Such a test generator will enable the exploration of a large number of conditions known to be necessary for the detection of the target fault. This will help decrease significantly the complexity of test generation by constraining the search.
Deliverables: