Task ID: 646.003
Start Date: October 1998 End Date: August 2001
Anticipated Primary Result
A list of crosstalk effects to be targeted for validation and low-complexity procedures to identify parts of a circuit where detailed extraction, validation, and test generation must be performed.
Background
Several new tools have been developed in recent years to accurately extract circuit parameters for deep-submicron technologies. To deal with the various effects caused by small feature sizes and their proximity, these techniques employ high complexity techniques that typically solve field equations with appropriate boundary conditions. In addition, the size of the extracted circuit model as well as the complexity of subsequent simulation is very high. Consequently, detailed extraction cannot be applied to an entire chip and circuit designers are often forced to manually identify parts of their chips for accurate extraction. Recently, tools have been developed that use the accurate extractors in a hierarchical fashion to decrease the complexity of extraction. In addition, areas of a circuit targeted for crosstalk analysis are selected manually. The proposed research will automatically identify an initial list of crosstalks to be targeted for validation. The proposed research will further decrease the overall complexity of extraction while ensuring minimal decrease in accuracy compared to that performed using an accurate model of the entire circuit compared to those performed on accurate models. Providing a low complexity tool that can efficiently use accurate extractors will decrease the involvement of circuit designers into extraction. This will help decrease the time required for extraction, validation, and test generation for crosstalk. It will also enhance the quality of validation and tests generated since it will use accurate extraction in all parts of the circuit where it is required, instead of in only the parts identified by the circuit designers.
Description
The key idea behind the approach to decrease the overall complexity of extraction is that the accuracy of extraction will be maximized for specific tasks, namely validation and test generation for crosstalk. The researchers propose to accomplish their objective by using an adaptive validation technique to determine where more accurate extraction is required. The validation will begin by using information about timing (delays, rise/fall times, slacks), types of logic (e.g. static vs. dynamic), device sizes, and first-order layout parasitics to identify an initial list of target crosstalks. Note that all these types of information can be obtained at very low computational complexity. Those validation targets for which the probability of a logical error is determined to be low will be eliminated. The team will develop techniques to perform increasingly more accurate extraction, test generation, and simulation-based validation for use with the remaining validation targets. As the test generation process proceeds for a given target, new line values are specified and gates and wires are added to the active part of the circuit under consideration. This information can be fed back to drive the extraction process. The new extracted values are then fed to the test generation system and used to either prune certain branches or continue the search in a new direction. The key issue that will be considered during this development will be identification of the computational complexity of extracting certain circuit parameters, the space complexity of the resulting circuit models, and their impacts on the accuracy and complexity of validation and test generation for crosstalk.
Deliverables: