Task ID: 867.001
Start Date: December 2000
Anticipated Primary Result
The first objective of this project is to extend a version of an existing crosstalk ATPG tool that can consider circuits containing certain types of complex gates, dynamic gates, and pass-transistor logic. Second, a divide-and-conquer technique will be developed to partition a chip into set of blocks and consider intra-block as well inter-block couplings. Third, the tools and techniques will be applied to real-life circuits to obtain detailed evaluation of the tools and techniques in terms of (a) their ability to generate vectors for a given crosstalk effect or prove it to be untestable, and (b) the usefulness of the generated vectors to direct redesign of the given circuit and influence design rules/practices for future designs. Finally, we will identify the way in which the proposed tools and techniques can be integrated into real-life design flows.
Background
We have been studying signal integrity problems in digital VLSI caused by capacitive cross coupling for the past 6-7 years. We have been working closely with several SRC companies for the last 3-4 years and our research has been funded by SRC for the last 2 years. During this period, we have developed theory of crosstalk, prototype tools for test generation for crosstalk, tools for efficient validation of crosstalk, a new tool called incremental timing refinement, and techniques to efficiently identify crosstalk effects that should be targeted for test generation for validation and/or test. The proposed research will begin with the tools that we have developed for single blocks of logic and enhance their capability to handle entire chips.
Description
In the first year of the project, our existing techniques will be extended and tools modified to (a) generate vectors for validation and/or test of a given list of crosstalk targets in a given block of logic that many contain certain types of complex and dynamic gates, and (b) to consider special cases of inter-block cross coupling, including coupling between a line in a bus and a line in an adjacent block of logic. The generated vectors will then be simulated extensively to identify the strengths and weaknesses of the techniques and tools. In the second year, the techniques and tools will be extended to (a) address the weaknesses identified in the first year, and (b) to handle large designs that contain logic blocks as well as semi-custom blocks, such as busses and memories. In the third year, we will perform extensive experiments to demonstrate the effectiveness of the techniques and tools. Besides its ability to distinguish between given targets that indeed cause errors from those that do not, we will also study the usefulness of the generated vectors in redesign. Finally, we will make recommendations about how the methodology for validation and test for cross coupling can be incorporated into real-life design flows.
Deliverables: