Task ID: 951.001
Continued from Task 646.001
Start Date: September 2001
Anticipated Primary Result
We will develop precise and surrogate fault models that capture crosstalk effects as aggravated by process variations and manufacturing defects. These models will capture both qualitative and quantitative effects. Subsequently, as described in Task 2, we will evaluate different fault models and identify the most suitable ones.
Background
Manufacturing defects can aggravate crosstalk noise to a point where they cause a well-designed circuit to fail. Classical delay tests as well as tests for crosstalk faults do not detect many of these new fault effects. The study of crosstalk effects in conjunction with manufacturing defects is hence essential to reduce defect-levels in chips shipped to customers. Development of appropriate qualitative and quantitative fault models is the crucial first step in this process. Faults in a precise fault model accurately capture the effects of realistic defects and the conditions for their detection. In contrast, faults in a surrogate fault model are selected such that a set of tests that detects a high proportion of the faults in the model is likely to detect a large proportion of chips with realistic defects.
Key challenges: Since crosstalk effects are timing dependent, it is necessary to consider the effects of defects on timing in a manner that minimizes the probability of test invalidation and maximizes the probability of identification of defective chips. The other key challenge is reigning in the complexities of test development as well as test application. Development of suitable fault models will constitute a crucial first step in meeting these challenges.
Description
We begin by logically injecting defects into layouts to determine how they affect circuit operation and to identify the conditions for their excitation and propagation of their effects. We will then classify the defects based on their characteristic, such as the number of defects (single or multiple), and the nature and size of their effects (gate/line delays and/or also crosstalk delays, and large or small delay). Each defect type, along with the conditions for excitation and propagation, defines an alternative precise fault model. Third, we will consider alternative types of targets to obtain additional alternative precise fault models. For example, for crosstalk delay with multiple defects, one can consider a set of targets. Here each target is comprised of a primary victim target path P from input to output, and a set of crosstalk sub-paths, each starting from an input and ending at one of the affecting lines that has a significant coupling with one of the lines along P. Precise fault models can eliminate the need to consider timing during test development at the cost of increasing the number of target faults. We will also consider a fault model where each combination of gates/lines with defects will constitute a separate target. For many types of defects, this will lead to fewer targets but require timing-oriented test generation and fault simulation. Fourth, we will consider simplified versions of the precise fault models to obtain surrogate fault models. Surrogate models will be based on (i) elimination of some targets from a precise fault model, and/or (ii) simplification of the conditions of excitation and propagation. The test generation and fault simulation frameworks described in Task 2 will be used to conduct experiments to identify those fault models that capture each type of defect at the least complexity.
Deliverables: