Task ID: 951.002
Continued from Task 646.002
Start Date: September 2001
Anticipated Primary Result
A framework will be developed for test generation and fault simulation for defect aggravated crosstalk and delay faults. These tools will be used in a detailed study of precise and surrogate fault models. Efficient ATPG and fault simulation tools will be developed for each of the resulting recommended fault models.
Background
Manufacturing defects can aggravate crosstalk effects to a point where they cause a well-designed circuit to fail. Generation and application of specific tests for defect-aggravated crosstalk is hence desired to reduce unnecessary loss of yield. More importantly, development of such tests is necessary to ensure low defect levels in chips shipped. Classical tests for delay faults are not adequate for detecting the types of effects targeted by this research. In fact, classical delay tests do not even cover a large fraction of the faults in their associated fault models. Thus a new generation of ATPG and fault simulation is required to handle effects that adversely affect the performance of a chip. One of the essential attributes of such an ATPG system is the ability to explicitly deal with delay and pulses in an accurate yet efficient manner. The tools to be developed in this project will be used to generate tests for defect-aggravated crosstalk and to help evaluate the various fault models to be proposed. Also, the generated tests can be used to augment stuck-at test sets and may even replace classical delay tests.
Description
We will develop a general framework for test generation that will encompass fault models identified in Task 1. This framework will be an extension of our current test generator to (i) work with an arbitrary value system, (ii) consider different types of targets and conditions for their detection, (iii) embody a general approach to handle the effect of defects on gate/line delays, and (iv) search the space of all possible vector pairs in alternative ways. We will also develop a framework for simulation for the proposed fault models. Issues to be addressed include estimation of the accuracy with which effects of target and non-target defects on timing are captured, metrics for coverage, and managing the complexity of fault simulation.
We will customize these tools for alternative fault models (precise and surrogate) by developing a suitable value system, an appropriate search strategy, and suitable heuristics. The tools will then be used to generate tests for each fault model and to compare the run time complexity of test generation verse test application. We will analyze how satisfaction of some conditions for detection of a target fault in a model can lead to satisfaction other conditions for its detection. We will analyze how the satisfaction of the conditions for detection of some targets often leads to the satisfaction of detection of other targets. These analyses will lead to validation of some of the surrogate fault models and, perhaps, to identification of better surrogate fault models. The results of the above analysis will be used to make final recommendations regarding suitable fault models. If possible, we will work with an industrial partner to develop a test chip and then test these chips using tests generated for various fault models. This will help us validate and refine, if necessary, our results.
Deliverables: