EXPERIENCES

• Research Assistant for DAPAR and SRC projects on "Crosstalk Validation and Test", USC, 95 - present.
• Implement parasitic extraction and circuit simulation based on level 1 and level 49 models.
• Research and develop a delay model
• Capturing the delay effects of simultaneous switching, input slew, input skew, output load, internal capacitances, coupling capacitances, and charge sharing.
• Applicable to advanced timing analysis and timing-oriented ATPG.
• Automate the generation of the developed delay model.
• Research and develop advanced timing analysis for partially-specified vectors.
• Research and develop timing-oriented ATPG: excitation/propagation logic conditions, timing implications and timing propagations, search strategies, using accurate timing model, considering timing as ranges.
• DFT Engineer at Intel Corporation, Santa Clara, May - Nov. 00.
• Develop and implement a tool flow for crosstalk test generation.
• Implement a crosstalk ATPG and investigate the impact of crosstalk effects.
• Illustrate the improvements of vector oriented methods over static validation methods.
• Identify modeling and algorithmic enhancements on crosstalk ATPG for industrial circuits.
• Member of Technical Staff at Intel Corporation, Santa Clara, May - Oct. 97.
• Case study on the problematic real circuit due to crosstalk.
• Research the input parameter corners for significant crosstalk effects.
• Develop techniques to reduce lookup tables of delay models to feasible sizes.
• Develop a multiple-input-variable curve-fitting to correctly capture the data trend.
• Develop a delay model for crosstalk pulse propagation.
• Teaching Assistant, USC, Jan. 95 - Dec. 00.
• VLSI design: device model, transistor characterization, resistance and capacitance extraction, design rule check, logic families, logical effort, clocking, Interconnect, adder/multiplier design, memory design, design methodologies, and layout issues.
• VLSI testing: fault modeling, fault simulation, test generation, design for testability, build-in self-test, and delay test.
• Physical design automation: partition, placement, floorplanning, global routing, detail routing, optimization algorithms, and performance-driven approaches.

SOFTWARE PROJECTS: C, C shell script, HSPICE, Perl

 

Parasitic extraction and circuit simulation (2000+ lines).

Automation of library characterization for capturing simultaneous switching effects (6000+ lines).

Timing analysis for partially-specified vectors (3000+ lines).

Test generation for high quality robust delay test (5000+ lines).

Crosstalk ATPG on industrial circuits (implemented 3500+ of 10000+ lines).

 

EDUCATIONS

• Current in Electrical Engineering, University of Southern California, Sept. 93 - present, Advisors:  Malvin A. Breuer and Sandeep Gupta (Expected graduate date: 05/01/03).
• M.S.Computer Science and Engineering, State University of New York at Buffalo, Sept. 91 - Jun. 93
• B.S. Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan, Sept. 86 - Jun. 90.

HONORS

• Honorable mentioned in EE Best Paper Award, USC 02.
• Nominated for the Best Paper Award in Asian Test Symposium, 00.
• First Prize in the thesis competition of Chinese Institute of Engineers, National Cheng-Kung University, Taiwan, May 90.